A semiconductor package mounts an integrated circuit die, and provides electrical and thermal connections between the die and an electronic subsystem, while also providing mechanical and environmental protection to the die. A ball grid array package performs these functions by mounting the die on a substrate. The electrical pads of the die are attached to conductive traces on the substrate. Electrical connections between the die and the substrate have been made by wirebond, solder balls, or TAB. The conductive traces on the substrate fanout from the die to an array of package pads. Each package pad has a package solder ball, which makes electrical contact to a pad on an electronic subsystem circuit board. The substrate is mounted flush to the circuit board, separated by the diameter of the package solder balls. The substrate has been fabricated in various technologies; such as printed wiring board, multilayer ceramic, or polyimide flex circuit.
A known problem with ball grid array package is mechanical fatigue of the package solder balls. There is a thermal coefficient of expansion (TCE) mismatch between the package and the circuit board. During power on/off cycles the package and board heat at different rates, and operate at different temperatures, so their expansion and contraction is not uniform. The difference in expansion causes strain across the package solder balls, resulting in reliability fails from fatigue. It is advantageous to match the TCE of the package to the TCE of the circuit board, thereby minimizing differences in expansion and the strain across the solderballs and reducing reliability failures from fatigue.
In a cavity up design the die is mounted on one side of the substrate and electrical connections to the circuit board are made on the opposite side of the substrate. The electrical connections between the die and the substrate are made by wirebond, TAB or solder balls. As the electrical connections to the die and the circuit board are on opposite sides, it is necessary to include and provide electrical vias through, and connecting both sides of the substrate. As the pitch of the array of package pads is reduced from 1.27 mm or 1.0 mm to 0.8 mm, 0.65 mm, or 0.5 mm, the through via consumes a larger percentage of area on the substrate. This blocks the routing of the conductive traces, and requires the use of a more expensive substrate technology.
For solder ball attached die there is also a TCE mismatch, this time between the die and the substrate. Again, it is advantageous to match both TCEs, the TCE of the die to the TCE of the substrate to reduce the fatigue failure of the die solder balls, and improve reliability. However, the TCE of a silicon die is 2 ppm/C and the TCE of a typical circuit board is 18 ppm/C, so it is not possible to match the TCE of the substrate to both the die and the circuit board. However it is beneficial to be able to engineer and design the TCE of the substrate to obtain optimum reliability.
Also for a solder ball attached die, the back of the die is exposed and a heatspreader may be attached to improve the thermal performance. The structure (substrate/die solder balls/die/adhesive/heatspreader) sandwiches the die between the substrate and the heatspreader. This sandwich structure is mechanically complex, and the components have different thermal TCE and often operate at different temperatures. Compared to a structure without a heatspreader, there is more stress on the die solder balls in the sandwich structure during thermal cycles and an increase in reliability failures. Again, it is beneficial to be able to engineer and design the TCE of the substrate to obtain optimum reliability.
There is a trade-off in adjusting the TCE of the substrate to match the die for improved die solder ball reliability and to match the circuit board for package solder ball reliability. Key factors when evaluating fatigue are the attached area (size of die and package) and the diameter of the solder balls (both die and package), which provide the separation between materials with different TCEs. When the pitch on the solder balls (die or package) is reduced, the diameter of the solder balls must also be reduced, and the distance is less between the materials with different TCEs. This reduced distance increases the stress on the solderballs, and therefore will cause higher fatigue for a given TCE mismatch. Therefore as technology shrinks it becomes increasingly beneficial to have the ability to engineer and design the TCE of the substrate for an optimum reliability.
In a cavity down design the same side of the package is used to mount the die and to make electrical connections to the circuit board. However, as the package is mounted flush to the circuit board, there is limited space to contain the integrated circuit die 10. Typically a hole is stamped, punched, or milled in the substrate 11 and then the substrate is attached to a support member 12 with an adhesive 13. The support member provides mechanical rigidity and is also a thermal heatspreader. The substrate is typically a polyimide flex circuit or a printed wiring board. The support member has a recess 14, which provides a space to contain the die. The multi-step process; fabricate substrate, excise hole, and laminate heatspreader increases package cost and design complexity. As an option, the support member is electrically connected to the substrate circuitry to improve performance. This electrical connection requires additional process steps and materials during the substrate attachment process, and therefore adds cost. In U.S. Pat. No. 5,420,460 (Massingill) the edge of the stamped hole 15a is outside the recess, and in U.S. Pat. No. 5,869,889 (Chia et al) the edge of the stamped hole 15b is inside the recess. The die is adhesively attached to the support member, and wirebonds 16 electrically connect the die to the circuitry on the substrate. The recess, die and wirebonds are coated with epoxy encapsulation 17 for environmental protection. Package solder balls 18 are attached to the array of package pads to complete the package.
The process of making the recess, removes a portion or all of the substrate in the recess area, and therefore removes the capability of having substrate circuitry in the total recess area. As the circuitry has been removed, the ability for attaching a die with solder balls is not available, and solder ball attached the die are not used.
As the clock rates and power of semiconductor die increase, power supply noise becomes a more serious problem. It becomes desirable to attach decoupling capacitors close to the die to minimize the effective inductances in the power supply distribution system. Approaches to accomplish this include mounting discrete capacitors on the subsystem circuit board adjacent to, or under the package, mounting discrete capacitors on the package, or providing thin organic dielectric layers in the package substrate. A drawback of discrete capacitors is the series inductance of the capacitors and the inductance from the routing to connect the capacitor limit its effectiveness to frequencies below 300 Mhz. A drawback of thin organic dielectric layers is the capacitance per unit area is small, typically less than 1 nF/cm^2, and is insufficient control power supply noise.
Consequently a need exists for a cavity-down ball grid array package, that allows substrate circuitry, does not have through vias, includes an integral electrically connected heatspreader that does not sandwich the die, mounts the die without a recess, allows electrical connections to the die with wirebond, TAB, or solder balls, allows the TCE of the substrate to be adjusted for optimum reliability, and provides a capacitor layer for controlling power supply noise.